1. Field of the Invention
The invention relates to a circuit arrangement for removing stuff bits from a frame-structured signal, which is available in n parallel bits, comprising
a) a memory circuit for storing the bits supplied in parallel, PA1 b) a controllable selection circuit having n outputs and coupled to the output of the memory circuit in the arrangement, and PA1 c) a control circuit having a control signal for determining the switching state of the selection circuit, and in that this switching state determines which of the bits stored in the memory circuit are applied to the n outputs of the selection circuit. PA1 d) the memory circuit comprises n delay elements for delaying each of the n parallel bits by the duration of one bit, PA1 e) if a maximum of p (p smaller than or equal to n) stuff bits can simultaneously occur among the n parallel bits, at predetermined intervals the control circuit will block the acceptance of new bits in p-1 delay elements out of the n delay elements. PA1 f) the selection circuit comprises cascades of addressable multiplexers, PA1 g) the control circuit comprises a modulo-n counting stuff bit counter whose count can be adjusted by means of a negative justification signal, PA1 h) the count of the stuff bit counter as well as the negative justification signal form addresses for the multiplexers, and PA1 i) the address inputs of the multiplexers of a cascade are arranged in parallel.
2. Related Art
Such a circuit arrangement is known from EP-A2-0 374 436. It is used, for example, in information transmission systems in which what is commonly referred to as stuff bits are inserted into the data signal having the lower clock rate to adapt the bit rates of two data signals which have different clock rates. These stuff bits do not represent any actual information and are again removed by an arrangement having the above characteristic features after the data have been transmitted. The stuff bits are situated at defined locations in the data signal. Most of these stuff bits have fixed positions and are necessary for a coarse frequency adjustment. A so-called variable stuff bit which is inserted into the data at irregular positions is used for fine frequency adjustment. The information whether a variable stuff bit is transmitted is also transmitted in the data signal as stuff information at a defined position. In the receiver the original data rate is recovered by removing all stuff bits and all further auxiliary information signals.
If stuff bits are to be removed from a serial data signal having a bit rate of the order of 140 Mbit/s, the complete circuit arrangement is to be structured in high-dissipative ECL technology. In order to reduce the dissipation, the serial data signal is converted into n parallel bit streams in a serial-to-parallel converter. If n is sufficiently large, the data streams can be processed in low-power CMOS technology after the conversion.
After the conversion of the serial data signal into n parallel bit streams there is the problem of extracting the stuff bits from the bit streams. For this purpose a memory circuit and a subsequent controllable selection circuit having n outputs is used according to EP-A2-0 374 436. The memory circuit of EP-A2-0 374 436 comprises at least 2n-1 memory cells. The control circuit which is used for adjusting the switching condition of the selection circuit is not described in detail. However, it is connected to the selection circuit over at least 2n-1 control lines so that an unrecognizable conversion of the stuff information signals into the control signals for the selection circuit is to take place in the control circuit.